Florent Kermarrec 51ce7cad6f sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2		2015-03-28 01:18:35 +01:00
..
com	liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6)	2015-03-22 11:11:37 +01:00
cpu	litescope: create example design derived from SoC that can be used on all targets	2015-02-28 22:19:24 +01:00
mem	sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2	2015-03-28 01:18:35 +01:00
others	move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)	2015-02-28 11:51:51 +01:00
soc	sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy	2015-03-25 16:57:38 +01:00
tools	liteeth: use bios ip_address in example designs	2015-03-18 18:18:43 +01:00
video	sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it	2015-03-02 08:36:39 +01:00
__init__.py	rename milkymist-ng to MiSoC	2013-11-09 15:27:32 +01:00