Florent Kermarrec 52fba05e26 sdram/phy/initsequence: add burst chop 4 (BC4) for DDR3 ... This is needed for half rate controllers with burst length of 4. For best efficiency quarter rate controllers should be used.		2015-08-04 11:19:20 +02:00
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core	sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon	2015-06-17 15:30:30 +02:00
frontend	wishbone2lasmi: fix "READ_DATA" state	2015-07-09 10:40:32 +02:00
phy	sdram/phy/initsequence: add burst chop 4 (BC4) for DDR3	2015-08-04 11:19:20 +02:00
test	global: more pep8	2015-04-13 18:02:26 +02:00
__init__.py	global: pep8 (replace tabs with spaces)	2015-04-13 16:19:55 +02:00
module.py	global: pep8 (E302)	2015-04-13 16:47:22 +02:00