162 lines
5.0 KiB
Python
162 lines
5.0 KiB
Python
from migen.genlib.io import DDROutput
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from migen.flow.plumbing import Multiplexer, Demultiplexer
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from migen.genlib.cdc import PulseSynchronizer
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from misoclib.com.liteeth.common import *
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from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIICRG
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from misoclib.com.liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
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from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
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modes = {
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"GMII": 0,
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"MII": 1
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}
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tx_pads_layout = [("tx_er", 1), ("tx_en", 1), ("tx_data", 8)]
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rx_pads_layout = [("rx_er", 1), ("dv", 1), ("rx_data", 8)]
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class LiteEthPHYGMIIMIITX(Module):
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def __init__(self, pads, mode):
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self.sink = sink = Sink(eth_phy_description(8))
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# # #
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gmii_tx_pads = Record(tx_pads_layout)
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gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads, pads_register=False)
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self.submodules += gmii_tx
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mii_tx_pads = Record(tx_pads_layout)
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mii_tx = LiteEthPHYMIITX(mii_tx_pads, pads_register=False)
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self.submodules += mii_tx
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demux = Demultiplexer(eth_phy_description(8), 2)
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self.submodules += demux
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self.comb += [
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demux.sel.eq(mode == modes["MII"]),
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Record.connect(sink, demux.sink),
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Record.connect(demux.source0, gmii_tx.sink),
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Record.connect(demux.source1, mii_tx.sink),
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]
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if hasattr(pads, "tx_er"):
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self.comb += pads.tx_er.eq(0)
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self.sync += [
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If(mode == modes["MII"],
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pads.tx_en.eq(mii_tx_pads.tx_en),
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pads.tx_data.eq(mii_tx_pads.tx_data),
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).Else(
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pads.tx_en.eq(gmii_tx_pads.tx_en),
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pads.tx_data.eq(gmii_tx_pads.tx_data),
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)
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]
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class LiteEthPHYGMIIMIIRX(Module):
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def __init__(self, pads, mode):
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self.source = source = Source(eth_phy_description(8))
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# # #
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pads_d = Record(rx_pads_layout)
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self.sync += [
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pads_d.dv.eq(pads.dv),
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pads_d.rx_data.eq(pads.rx_data)
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]
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gmii_rx = LiteEthPHYGMIIRX(pads_d)
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self.submodules += gmii_rx
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mii_rx = LiteEthPHYMIIRX(pads_d)
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self.submodules += mii_rx
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mux = Multiplexer(eth_phy_description(8), 2)
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self.submodules += mux
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self.comb += [
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mux.sel.eq(mode == modes["MII"]),
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Record.connect(gmii_rx.source, mux.sink0),
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Record.connect(mii_rx.source, mux.sink1),
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Record.connect(mux.source, source)
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]
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class LiteEthGMIIMIIModeDetection(Module, AutoCSR):
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def __init__(self, clk_freq):
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self.mode = Signal()
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self._mode = CSRStatus()
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# # #
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mode = Signal()
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update_mode = Signal()
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self.sync += \
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If(update_mode,
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self.mode.eq(mode)
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)
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self.comb += self._mode.status.eq(self.mode)
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# Principle:
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# sys_clk >= 125MHz
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# eth_rx <= 125Mhz
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# We generate ticks every 1024 clock cycles in eth_rx domain
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# and measure ticks period in sys_clk domain.
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# Generate a tick every 1024 clock cycles (eth_rx clock domain)
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eth_tick = Signal()
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eth_counter = Signal(10)
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self.sync.eth_rx += eth_counter.eq(eth_counter + 1)
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self.comb += eth_tick.eq(eth_counter == 0)
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# Synchronize tick (sys clock domain)
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sys_tick = Signal()
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eth_ps = PulseSynchronizer("eth_rx", "sys")
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self.comb += [
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eth_ps.i.eq(eth_tick),
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sys_tick.eq(eth_ps.o)
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]
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self.submodules += eth_ps
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# sys_clk domain counter
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sys_counter = Counter(24)
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self.submodules += sys_counter
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sys_counter.reset.eq(1),
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If(sys_tick,
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NextState("COUNT")
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)
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)
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fsm.act("COUNT",
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sys_counter.ce.eq(1),
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If(sys_tick,
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NextState("DETECTION")
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)
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)
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fsm.act("DETECTION",
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update_mode.eq(1),
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# if freq < 125MHz-5% use MII mode
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If(sys_counter.value > int((clk_freq/125000000)*1024*1.05),
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mode.eq(1)
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# if freq >= 125MHz-5% use GMII mode
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).Else(
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mode.eq(0)
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),
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NextState("IDLE")
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)
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class LiteEthPHYGMIIMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, clk_freq, with_hw_init_reset=True):
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self.dw = 8
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# Note: we can use GMII CRG since it also handles tx clock pad used for MII
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self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)
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mode = self.mode_detection.mode
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self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode == modes["MII"])
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self.submodules.tx = RenameClockDomains(LiteEthPHYGMIIMIITX(pads, mode), "eth_tx")
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self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIMIIRX(pads, mode), "eth_rx")
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self.sink, self.source = self.tx.sink, self.rx.source
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