68 lines
2.0 KiB
Python
68 lines
2.0 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.fsm import FSM, NextState
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from migen.bus import wishbone
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from misoclib.com.litepcie.common import *
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class LitePCIeWishboneBridge(Module):
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def __init__(self, endpoint, address_decoder):
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self.wishbone = wishbone.Interface()
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# # #
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port = endpoint.crossbar.get_slave_port(address_decoder)
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self.submodules.fsm = fsm = FSM()
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fsm.act("IDLE",
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If(port.sink.stb & port.sink.sop,
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If(port.sink.we,
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NextState("WRITE"),
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).Else(
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NextState("READ")
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)
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).Else(
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port.sink.ack.eq(port.sink.stb)
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)
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)
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fsm.act("WRITE",
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self.wishbone.adr.eq(port.sink.adr[2:]),
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self.wishbone.dat_w.eq(port.sink.dat[:32]),
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self.wishbone.sel.eq(0xf),
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(1),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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port.sink.ack.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("READ",
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self.wishbone.adr.eq(port.sink.adr[2:]),
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(0),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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NextState("COMPLETION")
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)
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)
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self.sync += \
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If(self.wishbone.stb & self.wishbone.ack,
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port.source.dat.eq(self.wishbone.dat_r),
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)
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fsm.act("COMPLETION",
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port.source.stb.eq(1),
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port.source.sop.eq(1),
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port.source.eop.eq(1),
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port.source.len.eq(1),
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port.source.err.eq(0),
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port.source.tag.eq(port.sink.tag),
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port.source.adr.eq(port.sink.adr),
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port.source.cmp_id.eq(endpoint.phy.id),
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port.source.req_id.eq(port.sink.req_id),
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If(port.source.ack,
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port.sink.ack.eq(1),
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NextState("IDLE")
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)
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)
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