162 lines
4.5 KiB
Python
162 lines
4.5 KiB
Python
from misoclib.com.liteusb.common import *
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from migen.actorlib.structuring import Pack, Unpack
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from migen.genlib.misc import Timeout
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class LiteUSBPacketizer(Module):
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def __init__(self):
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self.sink = sink = Sink(user_description(8))
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self.source = source = Source(phy_description(8))
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# # #
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# Packet description
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# - preamble : 4 bytes
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# - dst : 1 byte
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# - length : 4 bytes
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# - payload
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header = [
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# preamble
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0x5A,
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0xA5,
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0x5A,
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0xA5,
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# dst
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sink.dst,
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# length
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sink.length[24:32],
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sink.length[16:24],
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sink.length[8:16],
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sink.length[0:8],
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]
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header_unpack = Unpack(len(header), phy_description(8))
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self.submodules += header_unpack
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for i, byte in enumerate(header):
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chunk = getattr(header_unpack.sink.payload, "chunk" + str(i))
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self.comb += chunk.data.eq(byte)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(sink.stb & sink.sop,
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NextState("INSERT_HEADER")
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)
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)
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fsm.act("INSERT_HEADER",
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header_unpack.sink.stb.eq(1),
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source.stb.eq(1),
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source.data.eq(header_unpack.source.data),
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header_unpack.source.ack.eq(source.ack),
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If(header_unpack.sink.ack,
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NextState("COPY")
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)
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)
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fsm.act("COPY",
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source.stb.eq(sink.stb),
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source.data.eq(sink.data),
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sink.ack.eq(source.ack),
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If(source.ack & sink.eop,
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NextState("IDLE")
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)
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)
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class LiteUSBDepacketizer(Module):
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def __init__(self, clk_freq, timeout=10):
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self.sink = sink = Sink(phy_description(8))
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self.source = source = Source(user_description(8))
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# # #
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# Packet description
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# - preamble : 4 bytes
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# - dst : 1 byte
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# - length : 4 bytes
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# - payload
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preamble = Array(Signal(8) for i in range(4))
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header = [
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# dst
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source.dst,
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# length
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source.length[24:32],
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source.length[16:24],
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source.length[8:16],
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source.length[0:8],
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]
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header_pack = InsertReset(Pack(phy_description(8), len(header)))
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self.submodules += header_pack
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for i, byte in enumerate(header):
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chunk = getattr(header_pack.source.payload, "chunk" + str(i))
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self.comb += byte.eq(chunk.data)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.comb += preamble[0].eq(sink.data)
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for i in range(1, 4):
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self.sync += If(sink.stb & sink.ack,
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preamble[i].eq(preamble[i-1])
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)
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fsm.act("IDLE",
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sink.ack.eq(1),
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If((preamble[3] == 0x5A) &
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(preamble[2] == 0xA5) &
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(preamble[1] == 0x5A) &
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(preamble[0] == 0xA5) &
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sink.stb,
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NextState("RECEIVE_HEADER")
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),
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header_pack.source.ack.eq(1),
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)
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self.submodules.timeout = Timeout(clk_freq*timeout)
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self.comb += [
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self.timeout.reset.eq(fsm.ongoing("IDLE")),
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self.timeout.ce.eq(1)
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]
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fsm.act("RECEIVE_HEADER",
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header_pack.sink.stb.eq(sink.stb),
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header_pack.sink.payload.eq(sink.payload),
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If(self.timeout.reached,
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NextState("IDLE")
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).Elif(header_pack.source.stb,
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NextState("COPY")
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).Else(
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sink.ack.eq(1)
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)
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)
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self.comb += header_pack.reset.eq(self.timeout.reached)
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sop = Signal()
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eop = Signal()
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cnt = Signal(32)
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fsm.act("COPY",
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source.stb.eq(sink.stb),
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source.sop.eq(sop),
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source.eop.eq(eop),
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source.data.eq(sink.data),
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sink.ack.eq(source.ack),
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If((source.stb & source.ack & eop) | self.timeout.reached,
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NextState("IDLE")
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)
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)
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self.sync += \
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If(fsm.ongoing("IDLE"),
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cnt.eq(0)
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).Elif(source.stb & source.ack,
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cnt.eq(cnt + 1)
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)
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self.comb += sop.eq(cnt == 0)
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self.comb += eop.eq(cnt == source.length - 1)
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