Florent Kermarrec 59e99bfbcd soc/uart: add configurable UART FIFO depth.		2020-02-28 22:34:11 +01:00
..
boards	targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).	2020-02-28 09:48:48 +01:00
build	lattice/yosys: don't use quiet operation since logs are useful and for consistency with others build backends.	2020-02-28 08:32:29 +01:00
gen	gen/fhdl/verilog: fix signed init values	2020-01-12 22:06:35 +01:00
soc	soc/uart: add configurable UART FIFO depth.	2020-02-28 22:34:11 +01:00
tools	soc/uart: add configurable UART FIFO depth.	2020-02-28 22:34:11 +01:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00