This website requires JavaScript.
Explore
Help
Sign in
Hardware
/
litex
Watch
1
Star
0
Fork
You've already forked litex
0
mirror of
https://github.com/enjoy-digital/litex.git
synced
2025-01-04 09:52:26 -05:00
Code
Issues
Projects
Releases
Packages
Wiki
Activity
5a0358754d
litex
/
litex
History
Florent Kermarrec
5a0358754d
soc_core/soc_core_argdict: use inspect to get all parameters and simplify
2019-10-12 19:18:57 +02:00
..
boards
platforms/versa_ecp5: add serdes refclk/sma
2019-10-11 19:51:38 +02:00
build
build/generic_platform: only add sources if language is not None
2019-10-10 19:39:33 +02:00
gen
gen/fhdl/verilog: allow single element verilog inline attribute
2019-08-28 05:24:11 +02:00
soc
soc_core/soc_core_argdict: use inspect to get all parameters and simplify
2019-10-12 19:18:57 +02:00
tools
targets/sim: switch from shadow_base to io_regions
2019-10-09 10:38:22 +02:00
__init__.py
soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)
2019-09-30 23:41:07 +02:00