litex/litex
William D. Jones 5a2c92ba80 Add TinyFPGA platform based on Migen. 2017-12-27 00:00:05 +01:00
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boards Add TinyFPGA platform based on Migen. 2017-12-27 00:00:05 +01:00
build Add TinyFPGA platform based on Migen. 2017-12-27 00:00:05 +01:00
gen gen/fhdl/verilog: revert _printcomb_simulation and _printcomb_regular (needed for icarus simulation) and add Finish command 2017-09-13 13:47:25 +02:00
soc soc/integration/soc_core: add uart_name parameters (allow selecting uart without modifications in platform file) 2017-12-26 18:11:47 +01:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00