litex/migen/fhdl
Florent Kermarrec 1f1ff5a5e9 migen/fhdl/tools: fix rename_clock_domain when new == old
Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
2015-07-24 12:48:51 +02:00
..
__init__.py
bitcontainer.py
conv_output.py
decorators.py
edif.py
module.py
namer.py fhdl/verilog: add reserved keywords 2015-05-23 14:01:08 +02:00
simplify.py
specials.py fhdl/specials: add Keep SynthesisDirective 2015-06-23 16:14:42 +02:00
std.py
structure.py
tools.py migen/fhdl/tools: fix rename_clock_domain when new == old 2015-07-24 12:48:51 +02:00
tracer.py
verilog.py fhdl/verilog: add reserved keywords 2015-05-23 14:01:08 +02:00
visit.py