Florent Kermarrec a78ca2de92 build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog)		2019-04-19 09:18:25 +02:00
..
altera	build/altera: switch to sdc constraints, add add_false_path_constraints method	2019-04-16 16:57:23 +02:00
lattice	build/lattice/trellis: also generate bitstream in svf format	2019-03-06 16:29:18 -05:00
microsemi	build/microsemi/libero_soc: add linux build script support	2019-03-16 09:33:16 +01:00
sim	build/sim/core: Initialize Verilator commandArgs	2019-04-17 10:39:35 -04:00
xilinx	build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog)	2019-04-19 09:18:25 +02:00
__init__.py
generic_platform.py	generic_platform: use set for sources	2018-11-12 11:47:39 +01:00
generic_programmer.py	build: merge more migen changes	2018-11-12 11:26:35 +01:00
openocd.py	gen/build: merge with migen 0575c749e35a7180f0dca408e426af8eef22b568 and reintegrate migen simulator	2016-03-21 19:15:40 +01:00
tools.py	build: merge more migen changes	2018-11-12 11:26:35 +01:00