Florent Kermarrec 5aa516cb8d soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read. ... When UARTCrossover is used over Etherbone, acking data directly with the read avoid the write/read round-trip and speed up communication a lot (>10x).		2020-01-16 19:45:41 +01:00
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boards	targets/arty/genesys2: fix EthernetSoC/EtherboneSoC selection	2020-01-16 13:17:33 +01:00
build	Add optional 'ignore-loops' flag to nextpnr	2020-01-10 16:07:56 +01:00
gen	gen/fhdl/verilog: fix signed init values	2020-01-12 22:06:35 +01:00
soc	soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read.	2020-01-16 19:45:41 +01:00
tools	tools/litex_sim: use default integrated_rom_size	2020-01-13 17:39:23 +01:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00