Build your hardware, easily!
Go to file
Florent Kermarrec 5b0a8a798f add test_MigLa.py (Wip)
fixes
2012-09-14 14:08:20 +02:00
examples add test_MigLa.py (Wip) 2012-09-14 14:08:20 +02:00
migScope add test_MigLa.py (Wip) 2012-09-14 14:08:20 +02:00
sim Clean up 2012-09-09 23:46:26 +02:00
spi2Csr add test_MigLa.py (Wip) 2012-09-14 14:08:20 +02:00
README update README 2012-09-12 18:09:12 +02:00
top.py split migScope to trigger & recorder 2012-08-26 21:30:23 +02:00

README

[> migScope
------------

This is a small Logic Analyser to be embedded in a Fpga design to debug internal
or external signals.

[> Status:
Early development phase

Simulation:
-tb_spi2Csr      :   Test Spi <--> Csr Bridge : [Ok]
-tb_TriggerCsr   :   Test Trigger with Csr    : [Ok]
-tb_RecorderCsr  :   Test Recorder with Csr   : [Ok]
-tb_MigScope     :   Global Test with Csr     : [Ok]

Example Design:
-de0_nano        :   Generate Signals in FPGA and probe them with migScope : [Wip]
                     Toolchain [Ok]
-de1             :   Generate Signals in FPGA and probe them with migScope : [Wip]              
                     Toolchain [Ok]

[> Contact
E-mail: florent@enjoy-digital.fr