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litex/misoclib/mem/litesata/example_designs/targets
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Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
..
__init__.py litesata: move file and modify import to misoclib.mem.litesata 2015-02-28 11:03:24 +01:00
bist.py remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
core.py litesata: move file and modify import to misoclib.mem.litesata 2015-02-28 11:03:24 +01:00