Tim Callahan 5cb467cae3 Vexriscv "lite" uses "--mulDiv true", so enable "mul" instructions. ... Signed-off-by: Tim Callahan <tcal@google.com>		2021-02-14 14:16:14 -08:00
..
build	build/xilinx/symbiflow: fix bitstream_device select	2021-02-08 15:38:30 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	Vexriscv "lite" uses "--mulDiv true", so enable "mul" instructions.	2021-02-14 14:16:14 -08:00
tools	litex_term: support Intel/Altera nios2-terminal	2021-02-08 11:42:37 +07:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00