litex/litex
2019-11-15 10:57:31 +01:00
..
boards soc_sdram/kcu105: add optional main_ram_size_limit and use it on KCU105 to limit to 1GB instead of 2GB. 2019-11-07 09:00:54 +01:00
build build/sim: cleanup run_as_root 2019-11-15 10:57:31 +01:00
gen gen/fhdl/verilog: allow single element verilog inline attribute 2019-08-28 05:24:11 +02:00
soc bios/flash: minor cleanup on serialboot flashing, add flash address support 2019-11-09 00:05:36 +01:00
tools tools/litex_sim: cleanup/update (no functional change) 2019-11-14 11:19:23 +01:00
__init__.py soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00