litex/litex/boards/targets
2020-01-20 12:10:00 +01:00
..
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
arty.py targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) 2020-01-20 12:10:00 +01:00
de0nano.py SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets 2020-01-13 15:03:36 +01:00
genesys2.py targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) 2020-01-20 12:10:00 +01:00
kc705.py targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) 2020-01-20 12:10:00 +01:00
kcu105.py targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) 2020-01-20 12:10:00 +01:00
minispartan6.py SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets 2020-01-13 15:03:36 +01:00
netv2.py targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) 2020-01-20 12:10:00 +01:00
nexys4ddr.py targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) 2020-01-20 12:10:00 +01:00
nexys_video.py targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) 2020-01-20 12:10:00 +01:00
pcie_screamer.py SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets 2020-01-13 15:03:36 +01:00
simple.py targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) 2020-01-20 12:10:00 +01:00
ulx3s.py SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets 2020-01-13 15:03:36 +01:00
versa_ecp5.py targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) 2020-01-20 12:10:00 +01:00