60 lines
1.9 KiB
Python
60 lines
1.9 KiB
Python
from fractions import Fraction
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from migen.fhdl.structure import *
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from migen.fhdl.specials import Instance
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from migen.fhdl.module import Module
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class M1CRG(Module):
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def __init__(self, infreq, outfreq1x):
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self.clk50_pad = Signal()
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self.trigger_reset = Signal()
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self.eth_rx_clk_pad = Signal()
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self.eth_tx_clk_pad = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x_270 = ClockDomain()
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self.clock_domains.cd_sys4x_wr = ClockDomain()
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self.clock_domains.cd_sys4x_rd = ClockDomain()
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.clock_domains.cd_vga = ClockDomain()
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ratio = Fraction(outfreq1x)/Fraction(infreq)
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in_period = float(Fraction(1000000000)/Fraction(infreq))
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inst_items = [
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Instance.Parameter("in_period", in_period),
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Instance.Parameter("f_mult", ratio.numerator),
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Instance.Parameter("f_div", ratio.denominator),
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Instance.Input("clk50_pad", self.clk50_pad),
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Instance.Input("trigger_reset", self.trigger_reset),
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Instance.Input("eth_rx_clk_pad", self.eth_rx_clk_pad),
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Instance.Input("eth_tx_clk_pad", self.eth_tx_clk_pad),
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Instance.Output("sys_clk", self.cd_sys.clk),
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Instance.Output("sys_rst", self.cd_sys.rst),
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Instance.Output("clk2x_270", self.cd_sys2x_270.clk),
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Instance.Output("clk4x_wr", self.cd_sys4x_wr.clk),
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Instance.Output("clk4x_rd", self.cd_sys4x_rd.clk),
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Instance.Output("eth_rx_clk", self.cd_eth_rx.clk),
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Instance.Output("eth_tx_clk", self.cd_eth_tx.clk),
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Instance.Output("vga_clk", self.cd_vga.clk)
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]
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for name in [
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"norflash_rst_n",
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"clk4x_wr_strb",
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"clk4x_rd_strb",
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"ddr_clk_pad_p",
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"ddr_clk_pad_n",
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"eth_phy_clk_pad",
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"vga_clk_pad"
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]:
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s = Signal(name=name)
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setattr(self, name, s)
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inst_items.append(Instance.Output(name, s))
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self.specials += Instance("m1crg", *inst_items)
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