Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
litex/milkymist/m1crg/__init__.py

60 lines
1.9 KiB
Python
Raw Normal View History

Generate all clocks for the DDR PHY
2012-02-16 12:02:37 -05:00
from fractions import Fraction
from migen.fhdl.structure import *
Use new 'specials' API
2013-02-24 07:07:25 -05:00
from migen.fhdl.specials import Instance
Use new module, autoreg and eventmanager Migen APIs
2013-03-10 14:32:38 -04:00
from migen.fhdl.module import Module
Generate all clocks for the DDR PHY
2012-02-16 12:02:37 -05:00
Use new ClockDomain API
2013-03-15 14:17:05 -04:00
class M1CRG(Module):
Generate all clocks for the DDR PHY
2012-02-16 12:02:37 -05:00
def __init__(self, infreq, outfreq1x):
Use Mibuild
2013-02-11 12:23:06 -05:00
self.clk50_pad = Signal()
Generate all clocks for the DDR PHY
2012-02-16 12:02:37 -05:00
self.trigger_reset = Signal()
Use Mibuild
2013-02-11 12:23:06 -05:00
self.eth_rx_clk_pad = Signal()
self.eth_tx_clk_pad = Signal()
Use new ClockDomain API
2013-03-15 14:17:05 -04:00
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x_270 = ClockDomain()
self.clock_domains.cd_sys4x_wr = ClockDomain()
self.clock_domains.cd_sys4x_rd = ClockDomain()
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
self.clock_domains.cd_vga = ClockDomain()
Basic support for new clock domain and instance API
2012-09-10 17:47:06 -04:00
ratio = Fraction(outfreq1x)/Fraction(infreq)
in_period = float(Fraction(1000000000)/Fraction(infreq))
inst_items = [
Instance.Parameter("in_period", in_period),
Instance.Parameter("f_mult", ratio.numerator),
Instance.Parameter("f_div", ratio.denominator),
Use Mibuild
2013-02-11 12:23:06 -05:00
Instance.Input("clk50_pad", self.clk50_pad),
Basic support for new clock domain and instance API
2012-09-10 17:47:06 -04:00
Instance.Input("trigger_reset", self.trigger_reset),
Use Mibuild
2013-02-11 12:23:06 -05:00
Instance.Input("eth_rx_clk_pad", self.eth_rx_clk_pad),
Instance.Input("eth_tx_clk_pad", self.eth_tx_clk_pad),
Basic support for new clock domain and instance API
2012-09-10 17:47:06 -04:00
Instance.Output("sys_clk", self.cd_sys.clk),
Define clock domains instead of passing extra clocks as regular signals
2012-09-10 18:21:07 -04:00
Instance.Output("sys_rst", self.cd_sys.rst),
Instance.Output("clk2x_270", self.cd_sys2x_270.clk),
Instance.Output("clk4x_wr", self.cd_sys4x_wr.clk),
Instance.Output("clk4x_rd", self.cd_sys4x_rd.clk),
Use Mibuild
2013-02-11 12:23:06 -05:00
Instance.Output("eth_rx_clk", self.cd_eth_rx.clk),
Instance.Output("eth_tx_clk", self.cd_eth_tx.clk),
Define clock domains instead of passing extra clocks as regular signals
2012-09-10 18:21:07 -04:00
Instance.Output("vga_clk", self.cd_vga.clk)
Basic support for new clock domain and instance API
2012-09-10 17:47:06 -04:00
]
Generate all clocks for the DDR PHY
2012-02-16 12:02:37 -05:00
for name in [
Use Mibuild
2013-02-11 12:23:06 -05:00
"norflash_rst_n",
Prepare for new DDR PHY
2012-02-19 12:43:42 -05:00
"clk4x_wr_strb",
Add Ethernet MAC
2012-05-19 18:30:03 -04:00
"clk4x_rd_strb",
Use Mibuild
2013-02-11 12:23:06 -05:00
"ddr_clk_pad_p",
"ddr_clk_pad_n",
"eth_phy_clk_pad",
VGA framebuffer connections
2012-06-17 07:41:26 -04:00
"vga_clk_pad"
Connect DDR PHY Doesn't do much for the moment, just to check synthesis/P&R.
2012-02-17 05:04:44 -05:00
]:
Generate all clocks for the DDR PHY
2012-02-16 12:02:37 -05:00
s = Signal(name=name)
setattr(self, name, s)
Basic support for new clock domain and instance API
2012-09-10 17:47:06 -04:00
inst_items.append(Instance.Output(name, s))
Generate all clocks for the DDR PHY
2012-02-16 12:02:37 -05:00
Use new module, autoreg and eventmanager Migen APIs
2013-03-10 14:32:38 -04:00
self.specials += Instance("m1crg", *inst_items)