Sebastien Bourdeauducq 382ed013af minor cleanups		2015-04-02 14:40:29 +08:00
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core	minor cleanups	2015-04-02 14:40:29 +08:00
frontend	sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)	2015-03-02 10:59:43 +01:00
phy	sdram/phy/simphy: OK with DDR3	2015-03-28 01:59:55 +01:00
test	sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings.	2015-03-25 16:56:29 +01:00
__init__.py	…
module.py	sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue)	2015-03-28 16:35:15 +01:00