Build your hardware, easily!
Go to file
Florent Kermarrec 609f8f9abb revert submodules/specials/clock_domains syntax 2015-01-22 14:00:50 +01:00
miscope revert submodules/specials/clock_domains syntax 2015-01-22 14:00:50 +01:00
sim revert submodules/specials/clock_domains syntax 2015-01-22 14:00:50 +01:00
.gitignore add Setup.py / .gitignore 2012-09-18 00:22:52 +02:00
README use verilog namespace to export mila configuration 2014-08-03 17:09:01 +02:00
setup.py refactor code 2014-04-20 23:53:33 +02:00

README

             _____       _            ____  _     _ _       _ 
            |   __|___  |_|___ _ _   |    \|_|___|_| |_ ___| |
            |   __|   | | | . | | |  |  |  | | . | |  _| .'| |
            |_____|_|_|_| |___|_  |  |____/|_|_  |_|_| |__,|_|
                      |___|   |___|          |___|
 
       Copyright 2012-2014 / Florent Kermarrec / florent@enjoy-digital.fr
 
                                 Miscope
--------------------------------------------------------------------------------

[> Miscope
------------

Miscope is a small logic analyzer to embed in an FPGA.

While free vendor toolchains are generally used by beginners or for prototyping 
(situations where having a logic analyzer in the design is generally helpful) 
free toolchains are always provided without the proprietary logic analyzer 
solution... :(

Baseid on Migen, Miscope aims to provide a free, portable and flexible 
alternatve to vendor's solutions!

[> Specification:

Miscope provides Migen cores to embed in the design and Python drivers to control
the logic analyzer from the Host. Miscope automatically interconnects all cores 
to a CSR bus. When using Python on the Host, no needs to worry about cores register
mapping, importing miscope project gives you direct access to all the cores!

Miscope produces .vcd output files to be analyzed in your favorite waveform viewer.

Since Miscope also provides an Uart2Wishbone bridge, you only need 2 external Rx/Tx
pins to be ready to debug!

[> Status:
MiIo & Mila working on board with standard term.
RLE working on board.
RangeDetector and EdgeDector terms not tested.

[> Examples:
Have a look at http://github.com/Florent-Kermarrec/misoc-de0nano
test_miio.py : Led & Switch Test controlled by Python Host.
test_mila.py : Logic Analyzer controlled by Python Host.

[> Contact
E-mail: florent@enjoy-digital.fr