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litex/litex/gen
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Florent Kermarrec 8f54386aab gen/fhdl/module: Add some comments.
2023-08-24 09:17:35 +02:00
..
fhdl gen/fhdl/module: Add some comments. 2023-08-24 09:17:35 +02:00
genlib gen/genlib/misc/WaitTimer: Cast t to int and minor cosmetic cleanup. 2023-07-31 11:27:47 +02:00
sim gen/fhdl: Integrate namer from Migen to give us more flexibility on generated verilog names. 2022-05-06 16:04:24 +02:00
__init__.py litex/gen: Split common in common/context/reduce/signal. 2023-07-27 15:02:37 +02:00
common.py litex/gen: Add some comments. 2023-07-27 16:18:30 +02:00
context.py litex/gen: Add some comments. 2023-07-27 16:18:30 +02:00
reduce.py litex/gen: Split common in common/context/reduce/signal. 2023-07-27 15:02:37 +02:00
signal.py litex/gen: Add some comments. 2023-07-27 16:18:30 +02:00