enjoy-digital 62d939e85f Merge pull request #543 from antmicro/jboc/eeprom-sim ... litex/build/sim: add module for simulating SPD EEPROM		2020-05-28 16:46:34 +02:00
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cores	litex/build/sim: add module for simulating SPD EEPROM	2020-05-28 12:10:25 +02:00
doc	soc/doc/csr: allow CSRField.reset to be a Migen Constant.	2020-03-23 18:47:41 +01:00
integration	bios: add main bus and csr bus infos, use KiB/GiB.	2020-05-28 15:05:24 +02:00
interconnect	soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone.	2020-05-27 18:40:45 +02:00
software	bios: add main bus and csr bus infos, use KiB/GiB.	2020-05-28 15:05:24 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00