Sebastien Bourdeauducq 6f5bf0292e fhdl/verilog: create clock domains in deterministic order		2015-11-05 15:06:33 +08:00
..
build	Merge 'new' branch	2015-11-04 16:07:20 +08:00
fhdl	fhdl/verilog: create clock domains in deterministic order	2015-11-05 15:06:33 +08:00
genlib	genlib/fsm: fix return value of _get_register_control	2015-10-19 19:03:43 +08:00
sim	sim: fix case break	2015-10-20 17:18:33 +08:00
test	test: fix divider testbench	2015-10-19 19:41:18 +08:00
util	build: cleanup	2015-09-28 20:34:35 +08:00
__init__.py	simplify imports, migen.fhdl.std -> migen	2015-09-12 19:34:07 +08:00