97 lines
2.7 KiB
Python
97 lines
2.7 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.fhdl.specials import Special
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class DifferentialInput(Special):
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def __init__(self, i_p, i_n, o):
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Special.__init__(self)
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self.i_p = wrap(i_p)
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self.i_n = wrap(i_n)
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self.o = wrap(o)
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def iter_expressions(self):
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yield self, "i_p", SPECIAL_INPUT
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yield self, "i_n", SPECIAL_INPUT
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yield self, "o", SPECIAL_OUTPUT
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@staticmethod
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def lower(dr):
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raise NotImplementedError("Attempted to use a differential input, but platform does not support them")
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class DifferentialOutput(Special):
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def __init__(self, i, o_p, o_n):
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Special.__init__(self)
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self.i = wrap(i)
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self.o_p = wrap(o_p)
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self.o_n = wrap(o_n)
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def iter_expressions(self):
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yield self, "i", SPECIAL_INPUT
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yield self, "o_p", SPECIAL_OUTPUT
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yield self, "o_n", SPECIAL_OUTPUT
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@staticmethod
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def lower(dr):
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raise NotImplementedError("Attempted to use a differential output, but platform does not support them")
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class CRG(Module):
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def __init__(self, clk, rst=0):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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if hasattr(clk, "p"):
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clk_se = Signal()
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self.specials += DifferentialInput(clk.p, clk.n, clk_se)
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clk = clk_se
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# Power on Reset (vendor agnostic)
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int_rst = Signal(reset=1)
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self.sync.por += int_rst.eq(rst)
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self.comb += [
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self.cd_sys.clk.eq(clk),
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self.cd_por.clk.eq(clk),
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self.cd_sys.rst.eq(int_rst)
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]
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class DDRInput(Special):
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def __init__(self, i, o1, o2, clk=ClockSignal()):
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Special.__init__(self)
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self.i = wrap(i)
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self.o1 = wrap(o1)
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self.o2 = wrap(o2)
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self.clk = wrap(clk)
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def iter_expressions(self):
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yield self, "i", SPECIAL_INPUT
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yield self, "o1", SPECIAL_OUTPUT
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yield self, "o2", SPECIAL_OUTPUT
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yield self, "clk", SPECIAL_INPUT
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@staticmethod
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def lower(dr):
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raise NotImplementedError("Attempted to use a DDR input, but platform does not support them")
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class DDROutput(Special):
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def __init__(self, i1, i2, o, clk=ClockSignal()):
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Special.__init__(self)
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self.i1 = i1
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self.i2 = i2
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self.o = o
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self.clk = clk
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def iter_expressions(self):
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yield self, "i1", SPECIAL_INPUT
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yield self, "i2", SPECIAL_INPUT
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yield self, "o", SPECIAL_OUTPUT
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yield self, "clk", SPECIAL_INPUT
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@staticmethod
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def lower(dr):
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raise NotImplementedError("Attempted to use a DDR output, but platform does not support them")
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