89 lines
2.1 KiB
Python
89 lines
2.1 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.fhdl.bitcontainer import bits_for
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def split(v, *counts):
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r = []
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offset = 0
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for n in counts:
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if n != 0:
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r.append(v[offset:offset+n])
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else:
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r.append(None)
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offset += n
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return tuple(r)
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def displacer(signal, shift, output, n=None, reverse=False):
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if shift is None:
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return output.eq(signal)
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if n is None:
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n = 2**len(shift)
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w = len(signal)
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if reverse:
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r = reversed(range(n))
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else:
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r = range(n)
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l = [Replicate(shift == i, w) & signal for i in r]
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return output.eq(Cat(*l))
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def chooser(signal, shift, output, n=None, reverse=False):
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if shift is None:
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return output.eq(signal)
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if n is None:
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n = 2**len(shift)
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w = len(output)
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cases = {}
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for i in range(n):
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if reverse:
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s = n - i - 1
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else:
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s = i
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cases[i] = [output.eq(signal[s*w:(s+1)*w])]
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return Case(shift, cases).makedefault()
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def timeline(trigger, events):
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lastevent = max([e[0] for e in events])
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counter = Signal(max=lastevent+1)
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counterlogic = If(counter != 0,
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counter.eq(counter + 1)
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).Elif(trigger,
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counter.eq(1)
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)
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# insert counter reset if it doesn't naturally overflow
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# (test if lastevent+1 is a power of 2)
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if (lastevent & (lastevent + 1)) != 0:
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counterlogic = If(counter == lastevent,
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counter.eq(0)
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).Else(
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counterlogic
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)
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def get_cond(e):
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if e[0] == 0:
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return trigger & (counter == 0)
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else:
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return counter == e[0]
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sync = [If(get_cond(e), *e[1]) for e in events]
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sync.append(counterlogic)
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return sync
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class WaitTimer(Module):
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def __init__(self, t):
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self.wait = Signal()
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self.done = Signal()
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# # #
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count = Signal(bits_for(t), reset=t)
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self.comb += self.done.eq(count == 0)
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self.sync += \
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If(self.wait,
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If(~self.done, count.eq(count - 1))
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).Else(count.eq(count.reset))
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