Fin Maaß 280b6b4ee4 build: io: don't use mutable object as default value ... don't use mutable object (here: ClockSignal()) as default value, beacuse they will be the same object. Leeds to problems, when for example two `SDRInput` are used in two different Modules and one of them is used with a `ClockDomainsRenamer()`, then both are changed. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>		2024-09-30 15:18:11 +02:00
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build	build: io: don't use mutable object as default value	2024-09-30 15:18:11 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.	2024-07-03 21:44:31 +02:00
soc	soc/cores/vexriscv_smp: Add the generation of the default sim config (https://github.com/litex-hub/linux-on-litex-vexriscv/issues/405)	2024-09-25 10:38:37 +02:00
tools	Merge pull request #1974 from motec-research/dts_zephyr_updates	2024-09-17 14:58:51 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00