Florent Kermarrec 04017519c8 soc/interconnect/axi: add Wishbone2AXILite		2019-11-20 12:32:22 +01:00
..
__init__.py	add test directory with test_code_8b10b.py (from misoc)	2017-04-24 18:46:55 +02:00
test_axi.py	soc/interconnect/axi: add Wishbone2AXILite	2019-11-20 12:32:22 +01:00
test_bitbang.py	…
test_code_8b10b.py	…
test_csr.py	…
test_ecc.py	…
test_gearbox.py	test: add copyright header	2019-06-23 23:31:11 +02:00
test_hyperbus.py	soc/core: simplify/cleanup HyperRAM core	2019-08-16 14:04:58 +02:00
test_icap.py	soc/cores/icap: simplify ICAPBitstream (untested)	2019-10-01 21:30:14 +02:00
test_packet.py	test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer	2019-11-16 14:39:18 +01:00
test_prbs.py	…
test_spi.py	core/spi: add minimal SPISlave	2019-08-29 09:46:20 +02:00
test_targets.py	test/test_targets: skip Minerva test on Travis-CI, remove commented tests	2019-10-28 11:00:08 +01:00