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Build your hardware, easily!
11 Commits 37 Branches 13 Tags 47 MiB
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Python 43.2%
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Florent Kermarrec 674e0b3581 remove GTXE2_COMMON (we use in fact CPLL and not QPLL, GTXE2_COMMON was here in design just because of an old ISE bug) 
(see http://www.xilinx.com/support/answers/45410.html for more information)
 		2014-09-23 22:17:08 +02:00
lib/sata remove GTXE2_COMMON (we use in fact CPLL and not QPLL, GTXE2_COMMON was here in design just because of an old ISE bug) 2014-09-23 22:17:08 +02:00
platforms init with repo with simple TestDesign 2014-09-22 13:36:43 +02:00
targets init with repo with simple TestDesign 2014-09-22 13:36:43 +02:00
test init with repo with simple TestDesign 2014-09-22 13:36:43 +02:00
Makefile init with repo with simple TestDesign 2014-09-22 13:36:43 +02:00
README init with repo with simple TestDesign 2014-09-22 13:36:43 +02:00

README 

             _____       _            ____  _     _ _       _ 
            |   __|___  |_|___ _ _   |    \|_|___|_| |_ ___| |
            |   __|   | | | . | | |  |  |  | | . | |  _| .'| |
            |_____|_|_|_| |___|_  |  |____/|_|_  |_|_| |__,|_|
                      |___|   |___|          |___|
 
 	Copyright 2014 / Florent Kermarrec / florent@enjoy-digital.fr
 
                        Kintex-7 SATA PHY for M-Labs
--------------------------------------------------------------------------------

[> Getting started
------------------
1. Obtain MiSoC and follow its "Quick start guide". Set the MSCDIR environment
  variable to the MiSoC directory.

2. Build design:
  make all
  
3. Load design:
  make load

4. Run test:
  make test

[> Cores :
  - UART2Wishbone bridge
  - SATA PHY

[> Contact
E-mail: florent@enjoy-digital.fr