litex/misoclib
2015-03-01 11:21:12 +01:00
..
com liteXXX cores: share same methodology for on-board tests 2015-03-01 11:21:12 +01:00
cpu litescope: create example design derived from SoC that can be used on all targets 2015-02-28 22:19:24 +01:00
mem liteXXX cores: share same methodology for on-board tests 2015-03-01 11:21:12 +01:00
others move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future) 2015-02-28 11:51:51 +01:00
soc soc: fix register_rom 2015-02-28 23:51:51 +01:00
tools liteXXX cores: share same methodology for on-board tests 2015-03-01 11:21:12 +01:00
video video: reintegrate dvisampler from mixxeo (DVI/HDMI interfaces are common in today's SoCs) 2015-03-01 10:07:52 +01:00
__init__.py