litex/migen
Sebastien Bourdeauducq 683e6b4a6c record: support aligned flattening 2012-01-09 19:16:11 +01:00
..
bank Remove uses of declare_signal 2011-12-18 21:47:48 +01:00
bus csr: use optree 2011-12-22 19:36:56 +01:00
corelogic record: support aligned flattening 2012-01-09 19:16:11 +01:00
fhdl corelogic: FSM 2012-01-09 16:28:48 +01:00
flow record: preserve order 2012-01-09 15:14:42 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00