Sebastien Bourdeauducq
|
683e6b4a6c
|
record: support aligned flattening
|
2012-01-09 19:16:11 +01:00 |
|
Sebastien Bourdeauducq
|
b06e70d849
|
corelogic: FSM
|
2012-01-09 16:28:48 +01:00 |
|
Sebastien Bourdeauducq
|
47ae303846
|
record: cleanup
|
2012-01-09 15:20:09 +01:00 |
|
Sebastien Bourdeauducq
|
cef1c5d3af
|
record: better exception code
|
2012-01-09 15:17:24 +01:00 |
|
Sebastien Bourdeauducq
|
89bf704b2b
|
record: preserve order
|
2012-01-09 15:14:42 +01:00 |
|
Sebastien Bourdeauducq
|
bdcaeb159b
|
flow: draw network graph
|
2012-01-09 14:21:54 +01:00 |
|
Sebastien Bourdeauducq
|
d26ded93d8
|
flow: actor busy signal
|
2012-01-09 14:21:45 +01:00 |
|
Sebastien Bourdeauducq
|
d2d55372d8
|
Composer (WIP)
|
2012-01-08 13:56:11 +01:00 |
|
Sebastien Bourdeauducq
|
34c69db14a
|
endpoint: add _i/_o suffix on signal names
|
2012-01-07 21:21:46 +01:00 |
|
Sebastien Bourdeauducq
|
cdd9977a40
|
fhdl: better signal naming heuristic
|
2012-01-07 15:30:14 +01:00 |
|
Sebastien Bourdeauducq
|
b6763c28ea
|
constant: equality
|
2012-01-07 12:29:47 +01:00 |
|
Sebastien Bourdeauducq
|
7b395b565e
|
verilog: split comb block, use assign statements
|
2012-01-07 12:19:06 +01:00 |
|
Sebastien Bourdeauducq
|
f209bf6b33
|
convtools -> tools
|
2012-01-07 00:39:28 +01:00 |
|
Sebastien Bourdeauducq
|
0b195a244d
|
flow: network
|
2012-01-07 00:33:28 +01:00 |
|
Sebastien Bourdeauducq
|
3c1dada9cf
|
record: compatibility check
|
2012-01-06 23:00:23 +01:00 |
|
Sebastien Bourdeauducq
|
588f1a259e
|
flow: plumbing
|
2012-01-06 17:24:05 +01:00 |
|
Sebastien Bourdeauducq
|
8f1bf508ca
|
actor: simplified automatic control
|
2012-01-06 15:35:17 +01:00 |
|
Sebastien Bourdeauducq
|
a3bf877802
|
ALA: use records for tokens
|
2012-01-06 14:32:00 +01:00 |
|
Sebastien Bourdeauducq
|
038992e7d2
|
corelogic: record
|
2012-01-06 11:20:44 +01:00 |
|
Sebastien Bourdeauducq
|
d7a3bed44c
|
Signal repr
|
2012-01-06 11:20:33 +01:00 |
|
Sebastien Bourdeauducq
|
9366a226bb
|
Convert -> convert
|
2012-01-05 19:27:33 +01:00 |
|
Sebastien Bourdeauducq
|
edf90870c2
|
flow: sum and division actors
|
2011-12-23 00:35:53 +01:00 |
|
Sebastien Bourdeauducq
|
76db20cd9f
|
fhdl: encapsulate replicated constants
|
2011-12-23 00:35:13 +01:00 |
|
Sebastien Bourdeauducq
|
f0aac4b50f
|
flow: actor class
|
2011-12-22 19:37:16 +01:00 |
|
Sebastien Bourdeauducq
|
566295dea3
|
csr: use optree
|
2011-12-22 19:36:56 +01:00 |
|
Sebastien Bourdeauducq
|
ba40f58491
|
corelogic: operator tree
|
2011-12-22 15:46:19 +01:00 |
|
Sebastien Bourdeauducq
|
8a394f9159
|
verilog: comb reset
|
2011-12-22 00:04:53 +01:00 |
|
Sebastien Bourdeauducq
|
4d6be55e9f
|
verilog: break down Convert function
|
2011-12-21 23:08:50 +01:00 |
|
Sebastien Bourdeauducq
|
26e0b817e8
|
verilog: ignore variable property in combinatorial block
|
2011-12-21 23:00:36 +01:00 |
|
Sebastien Bourdeauducq
|
7456195775
|
Consistent names
|
2011-12-21 22:57:07 +01:00 |
|
Sebastien Bourdeauducq
|
94c5fba067
|
corelogic: fix signal exports
|
2011-12-18 21:54:28 +01:00 |
|
Sebastien Bourdeauducq
|
4f4d809a4e
|
fhdl: better matching of assignment
|
2011-12-18 21:49:48 +01:00 |
|
Sebastien Bourdeauducq
|
107f03fd4b
|
Remove uses of declare_signal
|
2011-12-18 21:47:48 +01:00 |
|
Sebastien Bourdeauducq
|
dd42b2daff
|
fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal
|
2011-12-18 21:47:29 +01:00 |
|
Sebastien Bourdeauducq
|
41e2430e2b
|
fhdl: automatic signal name from assignment
|
2011-12-18 21:26:51 +01:00 |
|
Sebastien Bourdeauducq
|
135a2eb868
|
bank: support raw registers
|
2011-12-18 00:28:04 +01:00 |
|
Sebastien Bourdeauducq
|
d21e095397
|
fhdl: fix series of if/elif/else
|
2011-12-17 20:31:42 +01:00 |
|
Sebastien Bourdeauducq
|
1a845d4553
|
32-device, 8-bit CSR bus
|
2011-12-17 15:54:49 +01:00 |
|
Sebastien Bourdeauducq
|
6f8a6db40a
|
verilog: get the simulator to run the combinatorial process at the beginning
|
2011-12-17 15:20:22 +01:00 |
|
Sebastien Bourdeauducq
|
ec47394012
|
verilog: support for float parameters in instances
|
2011-12-17 14:59:27 +01:00 |
|
Sebastien Bourdeauducq
|
ee6ca729a2
|
verilog: user-definable reset and clock
|
2011-12-16 22:25:05 +01:00 |
|
Sebastien Bourdeauducq
|
c7b9dfc203
|
fhdl: simpler syntax
|
2011-12-16 21:30:14 +01:00 |
|
Sebastien Bourdeauducq
|
39b7190334
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:55 +01:00 |
|
Sebastien Bourdeauducq
|
929cc98070
|
wishbone2csr: wait for WB deack
|
2011-12-13 17:38:59 +01:00 |
|
Sebastien Bourdeauducq
|
22d03b4943
|
timeline: only trigger in rest state
|
2011-12-13 15:25:46 +01:00 |
|
Sebastien Bourdeauducq
|
c840848dba
|
verilog: use blocking assignment in combinatorial process
|
2011-12-13 14:09:12 +01:00 |
|
Sebastien Bourdeauducq
|
92f24b784d
|
wishbone: decoder: fix slave cyc generation in registered mode
|
2011-12-13 14:08:39 +01:00 |
|
Sebastien Bourdeauducq
|
0ea7a9b2e6
|
wishbone2csr: fix double-write bug
|
2011-12-13 00:25:46 +01:00 |
|
Sebastien Bourdeauducq
|
923fc52e68
|
wishbone: only send ack to the active master in arbiter
|
2011-12-13 00:25:25 +01:00 |
|
Sebastien Bourdeauducq
|
a72faaecdd
|
fhdl: allow a namespace to be specified for Verilog conversion
|
2011-12-13 00:24:40 +01:00 |