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             / /  (_) /____ / __/ _ /_  __/ _ |
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      Copyright 2014-2015 The University of Hong Kong

        A small footprint and configurable SATA core
       developed for HKU by M-Labs Ltd & EnjoyDigital

[> Doc
---------
HTML : www.enjoy-digital.fr/litex/litesata/
PDF  : www.enjoy-digital.fr/litex/litesata.pdf

[> Intro
---------
LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.

LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex
FPGA IP cores by providing simple, elegant and efficient implementations of
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

The core uses simple and specific streaming buses and will provides in the future
adapters to use standardized AXI or Avalon-ST streaming buses.

Since Python is used to describe the HDL, the core is highly and easily
configurable.

The synthetizable BIST can be used as a starting point to integrate SATA in
your own SoC.

LiteSATA uses technologies developed in partnership with M-Labs Ltd:
 - Migen enables generating HDL with Python in an efficient way.
 - MiSoC provides the basic blocks to build a powerful and small footprint SoC.

LiteSATA can be used as a Migen/MiSoC library (by simply installing  it
with the provided setup.py) or can be integrated with your standard design flow
by generating the verilog rtl that you will use as a standard core.

[> Features
-----------
PHY:
  - OOB, COMWAKE, COMINIT
  - ALIGN inserter/remover and bytes alignment on K28.5
  - 8B/10B encoding/decoding in transceiver
  - Errors detection and reporting
  - 32 bits interface
  - 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)
Core:
  Link:
    - CONT inserter/remover
    - Scrambling/Descrambling of data
    - CRC inserter/checker
    - HOLD insertion/detection
    - Errors detection and reporting
  Transport/Command:
    - Easy to use user interfaces (Can be used with or without CPU)
    - 48 bits sector addressing
    - 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE
    - Errors detection and reporting

Frontend:
  - Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
  - Ports arbitration transparent to the user
  - Synthetizable BIST

[> Possibles improvements
-------------------------
- add standardized interfaces (AXI, Avalon-ST)
- add NCQ support
- add AES hardware encryption
- add on-the-flow compression/decompression
- add support for Altera PHYs.
- add support for Lattice PHYs.
- add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are
  supported)
- add Zynq Linux drivers.
- ... See below Support and Consulting :)

If you want to support these features, please contact us at florent [AT]
enjoy-digital.fr. You can also contact our partner on the public mailing list
devel [AT] lists.m-labs.hk.

[> Getting started
------------------
1. Install Python3 and Xilinx's Vivado software

2. Obtain Migen and install it:
  git clone https://github.com/m-labs/migen
  cd migen
  python3 setup.py install
  cd ..

3. Obtain LiteScope and install it:
  git clone https://github.com/enjoy-digital/litescope
  cd litescope
  python3 setup.py install
  cd ..

4. Obtain MiSoC:
  git clone https://github.com/m-labs/misoc --recursive
  XXX add setup.py to MiSoC for external use of misoclib?

5. Obtain LiteSATA
  git clone https://github.com/enjoy-digital/litesata

6. Build and load BIST design (only for KC705 for now):
  python3 make.py all (-s BISTSoCDevel to add LiteScopeLA)

7. Test design (only for KC705 for now):
  go to ./test directory and run:
  change com port in config.py to your com port
  python3 bist.py

8. Visualize Link Layer transactions (if BISTSoCDevel):
  go to ./test directory and run:
  python3 test_la.py [your_cond]
  your_cond can be wr_cmd, id_cmd, rd_resp, ...
  (open test_la.py to see all conditions or add yours)

9. If you only want to build the core and use it with your
  regular design flow:
  python3 make.py -t core build-core

[> Simulations:
  Simulations are available in ./lib/sata/test:
    - crc_tb
    - scrambler_tb
    - phy_datapath_tb
    - link_tb
    - command_tb
    - bist_tb
  hdd.py is a simplified HDD model implementing all SATA layers.
  To run a simulation, move to ./lib/sata/test and run:
    make simulation_name

[> Tests :
  A synthetizable BIST is provided and can be controlled with ./test/bist.py
  By using LiteScope and the provided ./test/test_link.py example you are able to
  visualize the internal logic of the design and even inject the captured data in
  the HDD model!

[> License
-----------
LiteSATA is released under the very permissive two-clause BSD license. Under the
terms of this license, you are authorized to use LiteSATA for closed-source
proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:
 - tell us that you are using LiteSATA
 - cite LiteSATA in publications related to research it has helped
 - send us feedback and suggestions for improvements
 - send us bug reports when something goes wrong
 - send us the modifications and improvements you have done to LiteSATA.

[> Support and Consulting
--------------------------
We love open-source hardware and like sharing our designs with others.

LiteSATA is developed and maintained by EnjoyDigital.

If you would like to know more about LiteSATA or if you are already a happy user
and would like to extend it for your needs, EnjoyDigital can provide standard
commercial support as well as consulting services.

So feel free to contact us, we'd love to work with you! (and eventually shorten
the list of the possible improvements :)

[> Contact
E-mail: florent [AT] enjoy-digital.fr