Florent Kermarrec 698bc88296 soc/interconnect/wishbone: allow setting adr_width (default to 30)		2019-05-02 09:34:30 +02:00
..
cores	cpu: use property methods to return name, endianness, gcc triple/flags, linker output format	2019-04-29 09:58:51 +02:00
integration	integration/soc_core: use cpu name as cpu-type for all cpus (mor1kx was instanciated with or1k)	2019-04-29 10:14:30 +02:00
interconnect	soc/interconnect/wishbone: allow setting adr_width (default to 30)	2019-05-02 09:34:30 +02:00
software	…
MISOC_LICENSE	…
__init__.py	…