Florent Kermarrec 698bc88296 soc/interconnect/wishbone: allow setting adr_width (default to 30)		2019-05-02 09:34:30 +02:00
..
boards	boards/platforms/ulx3s: fix default clock	2019-04-23 11:37:29 +02:00
build	build/sim: update tapcfg	2019-05-01 12:34:12 +02:00
gen	soc/integration: also add sha-1/date to generated software files	2019-04-23 13:17:54 +02:00
soc	soc/interconnect/wishbone: allow setting adr_width (default to 30)	2019-05-02 09:34:30 +02:00
tools	tools/remote/csr_builder: allow comments in csv file and cleanup	2019-04-24 12:25:49 +02:00
__init__.py	tools: move from litex.soc.tools to litex.tools and fix usb.core import	2019-04-20 10:44:53 +02:00