Florent Kermarrec 69f0035315 gen/fhdl: add Display for debug in simulation		2016-04-29 23:03:43 +02:00
..
boards	boards/targets: SDRAM modules are now litedram.modules	2016-04-29 19:05:23 +02:00
build	Make verilator build output error messages.	2016-04-19 16:02:26 +10:00
gen	gen/fhdl: add Display for debug in simulation	2016-04-29 23:03:43 +02:00
soc	soc/integration/soc_sdram: use new LiteDRAM names	2016-04-29 17:40:55 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00