226 lines
7.5 KiB
Python
226 lines
7.5 KiB
Python
from misoclib.mem.litesata.common import *
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class K7LiteSATAPHYCRG(Module):
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def __init__(self, clock_pads_or_refclk, pads, gtx, revision, clk_freq):
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self.tx_reset = Signal()
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self.rx_reset = Signal()
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self.ready = Signal()
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self.clock_domains.cd_sata_tx = ClockDomain()
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self.clock_domains.cd_sata_rx = ClockDomain()
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# CPLL
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# (sata_gen3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps
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# (sata_gen2 & sata_gen1) VCO still @ 3 GHz, Line rate is
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# decreased with output dividers.
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if isinstance(clock_pads_or_refclk, Signal):
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self.refclk = clock_pads_or_refclk
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else:
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self.refclk = Signal()
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clock_pads = clock_pads_or_refclk
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=clock_pads.refclk_p,
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i_IB=clock_pads.refclk_n,
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o_O=self.refclk
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)
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self.comb += gtx.gtrefclk0.eq(self.refclk)
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# TX clocking
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# (sata_gen3) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 300MHz (16-bits)
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# (sata_gen2) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 150MHz (16-bits)
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# (sata_gen1) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 75MHz (16-bits)
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mmcm_reset = Signal()
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mmcm_locked = Signal()
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mmcm_fb = Signal()
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mmcm_clk_i = Signal()
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mmcm_clk0_o = Signal()
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mmcm_div_config = {
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"sata_gen1": 16.0,
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"sata_gen2": 8.0,
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"sata_gen3": 4.0
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}
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mmcm_div = mmcm_div_config[revision]
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self.specials += [
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Instance("BUFG", i_I=gtx.txoutclk, o_O=mmcm_clk_i),
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Instance("MMCME2_ADV",
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p_BANDWIDTH="HIGH", p_COMPENSATION="ZHOLD", i_RST=mmcm_reset, o_LOCKED=mmcm_locked,
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# DRP
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i_DCLK=0, i_DEN=0, i_DWE=0, #o_DRDY=,
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i_DADDR=0, i_DI=0, #o_DO=,
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=6.666,
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p_CLKFBOUT_MULT_F=8.000, p_CLKFBOUT_PHASE=0.000, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=mmcm_clk_i, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
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# CLK0
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p_CLKOUT0_DIVIDE_F=mmcm_div, p_CLKOUT0_PHASE=0.000, o_CLKOUT0=mmcm_clk0_o,
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),
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Instance("BUFG", i_I=mmcm_clk0_o, o_O=self.cd_sata_tx.clk),
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]
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self.comb += [
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gtx.txusrclk.eq(self.cd_sata_tx.clk),
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gtx.txusrclk2.eq(self.cd_sata_tx.clk)
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]
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# RX clocking
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# (sata_gen3) sata_rx recovered clk @ 300MHz from GTX RXOUTCLK
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# (sata_gen2) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
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# (sata_gen1) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
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self.specials += [
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Instance("BUFG", i_I=gtx.rxoutclk, o_O=self.cd_sata_rx.clk),
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]
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self.comb += [
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gtx.rxusrclk.eq(self.cd_sata_rx.clk),
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gtx.rxusrclk2.eq(self.cd_sata_rx.clk)
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]
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# Configuration Reset
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# After configuration, GTX's resets have to stay low for at least 500ns
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# See AR43482
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startup_cycles = math.ceil(500*clk_freq/1000000000)
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startup_timer = WaitTimer(startup_cycles)
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self.submodules += startup_timer
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self.comb += startup_timer.wait.eq(~(self.tx_reset | self.rx_reset))
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# TX Startup FSM
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self.tx_ready = Signal()
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tx_startup_fsm = InsertReset(FSM(reset_state="IDLE"))
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self.submodules += tx_startup_fsm
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# Wait 500ns of AR43482
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tx_startup_fsm.act("IDLE",
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If(startup_timer.done,
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NextState("RESET_ALL"),
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)
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)
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# Reset CPLL, MMCM, GTX
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tx_startup_fsm.act("RESET_ALL",
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gtx.cpllreset.eq(1),
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mmcm_reset.eq(1),
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gtx.gttxreset.eq(1),
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NextState("RELEASE_CPLL"),
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)
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# Release CPLL reset and wait for lock
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tx_startup_fsm.act("RELEASE_CPLL",
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mmcm_reset.eq(1),
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gtx.gttxreset.eq(1),
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If(gtx.cplllock,
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NextState("RELEASE_MMCM"),
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)
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)
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# Release MMCM reset and wait for lock
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tx_startup_fsm.act("RELEASE_MMCM",
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gtx.gttxreset.eq(1),
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If(mmcm_locked,
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NextState("RELEASE_GTX")
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)
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)
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# Release GTX reset and wait for GTX resetdone
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# (from UG476, GTX is reseted on falling edge
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# of gttxreset)
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tx_startup_fsm.act("RELEASE_GTX",
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gtx.txuserrdy.eq(1),
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If(gtx.txresetdone,
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NextState("READY")
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)
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)
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# Start Delay alignment (Pulse)
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tx_startup_fsm.act("ALIGN",
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gtx.txuserrdy.eq(1),
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gtx.txdlyreset.eq(1),
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NextState("WAIT_ALIGN")
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)
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# Wait Delay alignment
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tx_startup_fsm.act("WAIT_ALIGN",
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gtx.txuserrdy.eq(1),
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If(gtx.txdlyresetdone,
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NextState("READY")
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)
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)
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tx_startup_fsm.act("READY",
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gtx.txuserrdy.eq(1),
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self.tx_ready.eq(1)
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)
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tx_ready_timer = WaitTimer(1*clk_freq//1000)
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self.submodules += tx_ready_timer
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self.comb += [
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tx_ready_timer.wait.eq(~self.tx_ready),
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tx_startup_fsm.reset.eq(self.tx_reset | tx_ready_timer.done),
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]
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# RX Startup FSM
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self.rx_ready = Signal()
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rx_startup_fsm = InsertReset(FSM(reset_state="IDLE"))
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self.submodules += rx_startup_fsm
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cdr_stable_timer = WaitTimer(2048)
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self.submodules += cdr_stable_timer
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# Wait 500ns of AR43482
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rx_startup_fsm.act("IDLE",
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If(startup_timer.done,
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NextState("RESET_GTX"),
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)
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)
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# Reset GTX
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rx_startup_fsm.act("RESET_GTX",
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gtx.gtrxreset.eq(1),
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NextState("WAIT_CPLL")
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)
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# Wait for CPLL lock
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rx_startup_fsm.act("WAIT_CPLL",
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gtx.gtrxreset.eq(1),
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If(gtx.cplllock,
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NextState("RELEASE_GTX")
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)
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)
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# Release GTX reset and wait for GTX resetdone
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# (from UG476, GTX is reseted on falling edge
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# of gttxreset)
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rx_startup_fsm.act("RELEASE_GTX",
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gtx.rxuserrdy.eq(1),
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cdr_stable_timer.wait.eq(1),
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If(gtx.rxresetdone & cdr_stable_timer.done,
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NextState("ALIGN")
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)
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)
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# Start Delay alignment (Pulse)
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rx_startup_fsm.act("ALIGN",
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gtx.rxuserrdy.eq(1),
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gtx.rxdlyreset.eq(1),
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NextState("WAIT_ALIGN")
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)
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# Wait Delay alignment
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rx_startup_fsm.act("WAIT_ALIGN",
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gtx.rxuserrdy.eq(1),
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If(gtx.rxdlyresetdone,
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NextState("READY")
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)
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)
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rx_startup_fsm.act("READY",
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gtx.rxuserrdy.eq(1),
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self.rx_ready.eq(1)
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)
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rx_ready_timer = WaitTimer(1*clk_freq//1000)
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self.submodules += rx_ready_timer
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self.comb += [
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rx_ready_timer.wait.eq(~self.rx_ready),
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rx_startup_fsm.reset.eq(self.rx_reset | rx_ready_timer.done),
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]
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# Ready
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self.comb += self.ready.eq(self.tx_ready & self.rx_ready)
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# Reset for SATA TX/RX clock domains
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self.specials += [
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AsyncResetSynchronizer(self.cd_sata_tx, ~(gtx.cplllock & mmcm_locked) | self.tx_reset),
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AsyncResetSynchronizer(self.cd_sata_rx, ~gtx.cplllock | self.rx_reset),
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]
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