litex/misoclib/mem/litesata/phy/k7
Florent Kermarrec 571ce5791a litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization
self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.
2015-06-10 12:14:48 +02:00
..
__init__.py litesata: create specialized kc705 platform to avoid duplicating things already in mibuild 2015-03-01 11:03:15 +01:00
crg.py litesata: do some cleanup and prepare for RAID 2015-05-23 14:08:56 +02:00
trx.py litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization 2015-06-10 12:14:48 +02:00