Florent Kermarrec 6a35337a09 gen/sim/vcd: allow continous update of vcd file and dynamic signals ... With continous update, VCD header needs to be writen at the beginning of the simulation. When a new signal is created, we rewrite the header and the content.		2016-05-28 10:25:48 +02:00
..
fhdl	gen/fhdl/structure: fix Display	2016-05-18 12:41:29 +02:00
genlib	gen/genlib/record: fix connect	2016-04-21 19:05:01 +02:00
sim	gen/sim/vcd: allow continous update of vcd file and dynamic signals	2016-05-28 10:25:48 +02:00
util	litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented	2015-11-13 14:44:16 +01:00
__init__.py	gen/build: merge with migen 0575c749e35a7180f0dca408e426af8eef22b568 and reintegrate migen simulator	2016-03-21 19:15:40 +01:00
MIGEN_LICENSE	litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented	2015-11-13 14:44:16 +01:00