mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
703b30e078
* fhdl/visit: determinism * structure/Case/makedefault: fix corner cases * fhdl/tools: apply lowerer to specials in deterministic order * fhdl/verilog: fix variable name conflict * fhdl/verilog: simpler names for IOs. Closes #40 * fhdl/namer: deterministic naming of signals with name_override * use https url for m-labs.hk * pipistrello: make PMOD an extension header * vivado: find clock nets by get_nets, not get_ports * build: support platform-independent false path designation * sim: add more signals to VCD (#36) * build/xilinx: fix error message when Xilinx toolchain directory exists but does not contain a ISE version directory. Closes #39 * kc705: make xadc an extension header * kc705: add xadc/ams gpios * Merge branch 'master' of github.com:m-labs/migen * conda: fix for conda-build > 1.19 * platforms/kc705: enable on-die termination for user_sma_clock * README: update * Revert "conda: use BUILDNUMBER from environment." This reverts commit b2eedfd2e24f0b83c2fb118a3f98cf349b256e91. * conda: use BUILDNUMBER from environment. * typo * Exception now has helpful string. * README: remove outdated build badge * sim: run MemoryToArray before lowering specials * fhdl/simplify/MemoryToArray: remove spurious memory ports from specials * sim: make unlowered specials an error * sim: lower specials, closes #34 * sim: support evaluating Replicate() * Revert "README.md->rst" * Prevent backslashes in (Windows) paths from being escaped by OpenOCD's TCL implementation. * Revert "conda: run tests as a part of package build." * Revert "setuptools: include examples as migen.examples." * Revert "test: also look for examples in [.../dist-packages]/migen/examples/." * conda: use source from the current checkout. * travis: disable (superseded by our buildbot). * test: also look for examples in [.../dist-packages]/migen/examples/. * setuptools: include examples as migen.examples. * conda: run tests as a part of package build. * build: return to current working directory after building * sim/vcd: support signals not appearing in FHDL * sim: deterministic clock iteration * sim: add support for passive generators * fhdl/structure: fix last test in _Value.__bool__ (a instead of b)
10 lines
298 B
Python
10 lines
298 B
Python
from litex.gen.fhdl.structure import *
|
|
from litex.gen.fhdl.module import *
|
|
from litex.gen.fhdl.specials import *
|
|
from litex.gen.fhdl.bitcontainer import *
|
|
from litex.gen.fhdl.decorators import *
|
|
|
|
from litex.gen.sim import *
|
|
|
|
from litex.gen.genlib.record import *
|
|
from litex.gen.genlib.fsm import *
|