Sebastien Bourdeauducq 6a412f796e xilinx_ise: add lock cycle to bitgen		2013-03-01 11:29:40 +01:00
..
platforms	platforms/m1: norflash_reset -> norflash_rst_n	2013-02-11 17:46:27 +01:00
__init__.py	Initial version	2013-02-07 22:07:30 +01:00
crg.py	Initial version	2013-02-07 22:07:30 +01:00
generic_platform.py	generic_platform/get_verilog: pass additional args to verilog.convert	2013-02-23 19:42:29 +01:00
tools.py	Support adding Verilog/VHDL files	2013-02-08 20:25:20 +01:00
xilinx_ise.py	xilinx_ise: add lock cycle to bitgen	2013-03-01 11:29:40 +01:00