Florent Kermarrec f58394f6af soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)		2015-03-01 18:25:47 +01:00
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__init__.py	uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)	2015-03-01 12:14:34 +01:00
serial.py	uart: use data instead of d on endpoint's layouts (coherency with others cores)	2015-03-01 16:56:48 +01:00
sim.py	soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)	2015-03-01 18:25:47 +01:00