Gwenhael Goavec-Merou f8acc5f506 litex/soc/cores/clock/xilinx_common: fix yosys synth: replace FD by FDCE		2022-01-25 21:44:02 +01:00
..
cores	litex/soc/cores/clock/xilinx_common: fix yosys synth: replace FD by FDCE	2022-01-25 21:44:02 +01:00
doc	doc: Fix doc build with Sphinx v1.x	2021-02-04 09:40:04 +01:00
integration	integration/builder: enable bios on gowin emcu	2022-01-23 11:02:36 +01:00
interconnect	interconnect/wishbone/axi: Automatically get InterconnectShared's shared data_width from first master.	2022-01-03 14:53:06 +01:00
software	software/bios: update comment	2022-01-23 16:57:33 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00