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litex/migen
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Guy Hutchison 28dde1e38f fhdl/verilog: add flag to produce ASIC-friendly output 2015-04-21 09:52:14 +08:00
..
actorlib global: pep8 (E225) 2015-04-13 21:11:13 +02:00
bank global: pep8 (E261, E271) 2015-04-13 21:21:30 +02:00
bus global: more pep8 2015-04-13 21:33:44 +02:00
fhdl fhdl/verilog: add flag to produce ASIC-friendly output 2015-04-21 09:52:14 +08:00
flow global: pep8 (E302) 2015-04-13 20:45:35 +02:00
genlib global: pep8 (E261, E271) 2015-04-13 21:21:30 +02:00
sim global: pep8 (E302) 2015-04-13 20:45:35 +02:00
test global: pep8 (E302) 2015-04-13 20:45:35 +02:00
util global: pep8 (E302) 2015-04-13 20:45:35 +02:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00