Nina Engelhardt 61b8958953 fix synthesis translate on/off switch		2013-07-26 15:55:16 +02:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
decorators.py	fhdl: RenameClockDomains decorator	2013-07-26 15:42:14 +02:00
module.py	fhdl: RenameClockDomains decorator	2013-07-26 15:42:14 +02:00
namer.py	New 'specials' API	2013-02-22 17:56:35 +01:00
size.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
specials.py	fhdl/specials/Instance: fix item sorting	2013-07-26 14:00:29 +02:00
std.py	fhdl: RenameClockDomains decorator	2013-07-26 15:42:14 +02:00
structure.py	fhdl: do not export Fragment	2013-07-25 18:52:54 +02:00
tools.py	fhdl/tools: do not export resort_statements	2013-07-17 16:50:09 +02:00
tracer.py	bank: automatic register naming	2013-03-12 15:45:24 +01:00
verilog.py	fix synthesis translate on/off switch	2013-07-26 15:55:16 +02:00
visit.py	fhdl: do not export Fragment	2013-07-25 18:52:54 +02:00