litex/migen
Sebastien Bourdeauducq 6ba0d4bd0d bus/wishbone: configurable data width 2013-07-27 22:25:07 +02:00
..
actorlib actorlib/spi: remove unused function 2013-07-27 15:36:42 +02:00
bank New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
bus bus/wishbone: configurable data width 2013-07-27 22:25:07 +02:00
fhdl fix synthesis translate on/off switch 2013-07-26 15:55:16 +02:00
flow flow/actor/PipelinedActor: clean up 2013-07-12 18:52:34 +02:00
genlib genlib/record: support abstract signal width 2013-07-27 22:18:06 +02:00
pytholite pytholite/io: len -> flen 2013-07-27 15:38:48 +02:00
sim fhdl: do not export Fragment 2013-07-25 18:52:54 +02:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00