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https://github.com/enjoy-digital/litex.git
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a2b71fde4a
A CSR bus data-width of 32 has been validated on very various design and is now recommended. It provides better performance without impacting resource usage (even on iCE40).
104 lines
3.9 KiB
Text
104 lines
3.9 KiB
Text
[> 2020.XX, planned for December 2020
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---------------------------------
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[> Issues resolved
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------------------
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- fix SDCard writes.
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- fix crt0 .data initialize on SERV/Minerva.
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[> Added Features
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------------------
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- Wishbone2CSR: add registered version and use it on system with SDRAM.
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- litex_json2dts: add Mor1kx DTS generation support.
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- Build: add initial Radiant support for NX FPGA family.
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- SoC: allow ROM to be optionally writable (for contents overwrite over UARTBone/Etherbone).
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- LiteSDCard: improve BIOS support.
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- UARTBone: add clock domain support.
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- Clocking: uniformize reset on iCE40PLL/ECP5PLL.
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- LiteDRAM: improve calibration and add BIOS debug commands.
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- Clocking: add initial Ultrascale+ support.
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- Sim: Allow dynamic enable/disable of tracing.
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- BIOS: improve memtest and report.
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- BIOS: rename/reorganize commands.
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- litex_server: simplify usage with PCIe and add debug parameter.
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- LitePCIe: add Ultrascale(+) support up to Gen3 X16.
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[> API changes/Deprecation
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--------------------------
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- BIOS: commands have been renamed/reorganized.
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- LiteDRAM: rdcmdphase/wrcmdphase no longer exposed.
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- CSR: change default csr_data_width from 8 to 32.
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[> 2020.08, planned for July 2020
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---------------------------------
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[> Issues resolved
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------------------
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- Fix flush_cpu_icache on VexRiscv.
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- Fix `.data` section placed in rom (#566)
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[> Added Features
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------------------
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- Properly integrate Minerva CPU.
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- Add nMigen dependency.
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- Pluggable CPUs.
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- BIOS history, autocomplete.
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- Improve boards's programmers.
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- Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
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- Speedup Memtest using an LFSR.
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- Add LedChaser on boards.
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- Improve WishboneBridge.
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- Improve Diamond constraints.
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- Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
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- Add CV32E40P CPU support (ex RI5CY).
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- JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
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- Add Symbiflow experimental support on Arty.
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- Add SDCard (SPI and SD modes) boot from FAT/exFAT filesystems with FatFs.
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- Simplify boot with boot.json configuration file.
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- Revert to a single crt0 (avoid ctr/xip variants).
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- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
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- Add AXI-Lite bus standard support.
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- Add VexRiscv SMP CPU support.
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[> API changes/Deprecation
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--------------------------
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- Add --build --load arguments to targets.
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- Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
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- Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
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- Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
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- Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
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- Rename --gateware-toolchain target parameter to --toolchain.
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- Integrate Zynq's PS7 as a regular CPU (zynq7000) and deprecate SoCZynq.
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[> 2020.04, released April 28th, 2020
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-------------------------------------
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[> Description
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--------------
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First release of LiteX and the ecosystem of cores!
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LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
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Cores/SoCs (with or without CPU).
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The common components of a SoC are provided directly:
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- Buses and Streams (Wishbone, AXI, Avalon-ST)
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- Interconnect
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- Common cores (RAM, ROM, Timer, UART, etc...)
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- CPU wrappers/integration
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- etc...
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And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
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PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
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It also provides build backends for open-source and vendors toolchains.
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[> Issues resolved
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------------------
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- NA
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[> Added Features
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------------------
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- NA
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[> API changes/Deprecation
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--------------------------
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- https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.
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