Marek Czerski 6eaa426e37 liteeth: allow to specify nrxslots and ntxslots for liteeth		2021-03-18 09:24:48 +01:00
..
build	build/generic_platform: Minor cosmetic cleanups.	2021-03-10 19:21:02 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	liteeth: allow to specify nrxslots and ntxslots for liteeth	2021-03-18 09:24:48 +01:00
tools	liteeth: allow to specify nrxslots and ntxslots for liteeth	2021-03-18 09:24:48 +01:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00