litex/litex/soc
2020-11-23 17:50:31 +01:00
..
cores add a hook for activating the GSR inside the STARTUPE2 block for spi_opi 2020-11-24 00:27:18 +08:00
doc soc: change default CSR bus data-width to 32. 2020-10-07 16:38:49 +02:00
integration integration/soc/add_etherbone: expose buffer_depth. 2020-11-23 17:50:31 +01:00
interconnect interconnect/csr/EventManager: simpifly/cleanup code that documents CSRs and always enable documentation. 2020-11-18 13:06:55 +01:00
software soc: rename HAS_TIMESTAMP to WITH_BUILD_TIME. 2020-11-18 22:04:14 +01:00
__init__.py