litex/migen
Alain Péteut 96bff77c36 add examples tests 2015-05-01 00:50:17 +08:00
..
actorlib migen/actorlib/packet: add Packetizer and Depacketizer 2015-04-28 18:44:05 +02:00
bank global: pep8 (E261, E271) 2015-04-13 21:21:30 +02:00
bus global: more pep8 2015-04-13 21:33:44 +02:00
fhdl migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb) 2015-04-24 12:54:08 +02:00
flow global: pep8 (E302) 2015-04-13 20:45:35 +02:00
genlib migen/genlib: avoid use of floating point in reverse_bytes 2015-04-27 21:04:18 +02:00
sim global: pep8 (E302) 2015-04-13 20:45:35 +02:00
test add examples tests 2015-05-01 00:50:17 +08:00
util global: pep8 (E302) 2015-04-13 20:45:35 +02:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00