litex/migen
Lars-Peter Clausen 72579a6129 Add support for negative slice indices
In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].

Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
	reg.eq(Cat(Replicate(0, n), reg[-n:])

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 21:56:01 +01:00
..
actorlib corelogic -> genlib 2013-02-22 23:19:37 +01:00
bank bank/description: memprefix 2013-02-25 23:14:15 +01:00
bus csr/SRAM: support for writes with memory widths larger than bus words 2013-03-09 00:50:57 +01:00
fhdl Add support for negative slice indices 2013-03-12 21:56:01 +01:00
flow corelogic -> genlib 2013-02-22 23:19:37 +01:00
genlib genlib: clock domain crossing elements 2013-02-23 19:03:35 +01:00
pytholite corelogic -> genlib 2013-02-22 23:19:37 +01:00
sim New 'specials' API 2013-02-22 17:56:35 +01:00
uio uio/ioo: fix specials 2013-02-25 23:13:38 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00